1. Technical Field
Embodiments relate to the determination of local mechanical stress induced in a semiconductor material wafer supporting interconnection levels on one surface when vias crossing the wafer are formed.
2. Discussion of the Related Art
During certain semiconductor wafer processings, mechanical stress may appear in the wafer and in different elements formed inside and on top of it. Further, such stress may appear due to temperature variations to which the wafer is subsequently submitted, and/or during the use of chips obtained from this wafer.
FIG. 1 is a cross-section view of a semiconductor wafer 1 having its rear surface supporting interconnection levels 2, comprising an insulating material 3 and metallizations, a single metallization, 4, being shown. This semiconductor wafer has been thinned and an opening has been formed from the front surface all the way to metallization 4. A conductive material 5, for example, a metal layer, for example, copper, has been deposited on the walls and the bottom of the opening. The opening can then be filled or not with a material 6, for example, an insulating polymer. Conductive material 5 and insulating filling material 6 form a via crossing the semiconductor wafer, which enables to access metallization 4.
As an example, the diameter of the vias may range between one and one thousand micrometers, and their depth may vary from some ten to several hundreds of micrometers.
In structures such as that shown in FIG. 1, significant levels of mechanical stress may appear, mainly at the bottom of the vias. Such significant mechanical stress levels are capable of deteriorating material 5 of the vias and of adversely affecting, after several uses, the proper electric operation of devices formed from the semiconductor wafer. Issues of electric and mechanical reliability of the devices may arise. It is desirable to be able to measure the mechanical stress induced in a semiconductor wafer after a specific processing to determine manufacturing methods, natures of materials, and layer thicknesses capable of decreasing this stress.
Existing methods for measuring the mechanical stress present in semiconductor wafers after they have, for example, been submitted to the forming of vias require sawing the semiconductor wafer to access the regions where the stress is desired to be measured. Such measurement methods, for example, are micro-Raman spectroscopy to determine the stress in silicon, X-ray diffraction to determine the stress in metal, or the so-called Digital Image Speckle Correlation (DISC) technique.
Such conventional measurement methods suffer from a main disadvantage, which is the need to saw the semiconductor wafer before the measurement. Now, the stress to be measured is partly released or modified on sawing of the semiconductor wafer. The stress which was present in the structure before the sawing of the wafer is thus no longer measured after the sawing.
Methods enabling to accurately determine the stress induced in a semiconductor material wafer having a surface supporting interconnection levels in the forming of vias crossing the wafer are thus needed.